CODEWITHSUNDEEP
vhdl
user1320084
user1320084

Reputation: 25

if statement in VHDL

I've got a question about the if statement in VHDL, see the example bellow;-) 

   signal SEQ : bit_vector(5 downto 0); 
signal output: bit; 
    -------

     if(SEQ = "000001") and (CNT_RESULT = "111111") then 
       output<= '1';
      CNT_RESET <= '0';
      else output<='0';
    end if;

and I get : the if statment is illegal and that "output" has multiply sources. any ideas

Upvotes: 2

Views: 26808

Answers (2)

Philippe
Philippe

Reputation: 3730

You are probably using an IF statement in the architecture body (which is a concurrent region). That's illegal. You need to put a process around it, so that it is in a sequential region (code is not tested!):

  process(seq, CNT_RESULT)
     if(SEQ = "000001") and (CNT_RESULT = "111111") then 
       output<= '1';
      CNT_RESET <= '0';
      else output<='0';
    end if;
  end process;

Upvotes: 3

sonicwave
sonicwave

Reputation: 6092

I presume the if statement is not inside a process? You can only use if statements inside a process. For similar functionality outside a process, you can use when:

output <= '1' when (SEQ = "000001") and (CNT_RESULT = "111111") else
          '0';

CNT_RESET <= '0' when (SEQ = "000001") and (CNT_RESULT = "111111") else
             '1';

Upvotes: 5

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