CODEWITHSUNDEEP
implementationvhdlfpga
xx77aBs
xx77aBs

Reputation: 4768

VDHL - initial value of signal?

I have simple VHDL modul that outputs PWM signal. PWM modul has signal that holds current PWM percentage. When I synthesize and implement it, that signal is reset by default to 0. Is there any way to configure it that after implementation PWM percentage is 20 or something else ?

Thanks !

Upvotes: 0

Views: 1098

Answers (2)

Ben Voigt
Ben Voigt

Reputation: 283624

You should be able to set the power-up default value. It has to agree with the reset value (if there is one) because the synthesizer will use NOT-gate-pushback to implement it.

Try

SIGNAL dutycycle : INTEGER := 20;   -- powerup value

PROCESS (n_reset, clk)
BEGIN
   IF TO_X01(n_reset) = '0' THEN
       dutycycle <= 20;             -- asynchronous reset value
   ELSIF RISING_EDGE(clk) THEN
       dutycycle <= load_dutycycle; -- synchronous load
   END IF;
END PROCESS;

Upvotes: 6

Gustavo Vargas
Gustavo Vargas

Reputation: 2597

You can put a reset input to your module that loads a default value into your percentage register.

Upvotes: 2

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