CODEWITHSUNDEEP
c++cgccmakefilec-preprocessor
iammilind
iammilind

Reputation: 69958

Running preprocessor based on using make command or makefile

In GCC we can run simple preprocessor as:

g++ -E x.cpp > temp.cpp

However, in larger projects where there are so many makefiles in place; it's very cumbersome to mention all the dependencies. E.g.

g++ -I /home/x1 -I /home/x2 ... -DMACRO1 -DMACRO2 ... -E x.cpp > temp.cpp

Is there any way by which using the makefile, we can run the C preprocessor ?

Upvotes: 3

Views: 5832

Answers (2)

DaveS
DaveS

Reputation: 511

Can't you use -save-temps? If your project has lots of makefiles, perhaps there's a top level one which defines the name / path to the compiler? I'd just hijack that to look something like:

CC = some-target-gcc -save-temps

Then you'll end up with a pile of .i files every time you build.

Upvotes: 3

William Morris
William Morris

Reputation: 3684

Using the suffix .cpp for the pre-processed file is a bad idea as it clashes with the .cpp suffix of your C++ files. Try something else - here's a snippet you can start with that uses the suffix .e:

CXX      = g++
CPPFLAGS = -E
CXXFLAGS = -Wall -DMACRO1 -DMACRO2
INCLUDES = -I /home/x1 -I /home/x2

%.e : %.c
        $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(INCLUDES) $< -o $@

Be careful to put a TAB at the start of the 'recipe' (the line "$(CXX) $(CFLAGS) ..."). The stuff above defines a rule that tells make how to build a .e file from a .cpp file. With a file x.cpp you can use

make x.e

Notice that the -E flag is defined in CPPFLAGS. This tells the compiler (g++) to stop after the preprocessing stage. The -o tells the compiler where to put the generated file, while the $@ is make shorthand for the target, in this case the .e file. There is no need to redirect anything; g++ writes the .e file for you.

If you want to generate a .e file for a list of cpp files, do something like:

SRCS = a.cpp b.cpp c.cpp d.cpp
CPPS = $(SRCS:.cpp=.e)   

.PHONY:cpps
cpps: $(CPPS)

Then build them:

make cpps

Upvotes: 1

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