CODEWITHSUNDEEP
arm
stone
stone

Reputation:

Does anyone know how to enable ARM FIQ?

Does anyone know how to enable ARM FIQ?

Upvotes: 5

Views: 5538

Answers (2)

ali-hussain
ali-hussain

Reputation: 511

The FIQ can be closed off to you by the chip manufacturer using trustzone extensions.

Trustzone creates a Secure world and a normal world. The secure world has its own supervisor, user and memory space. The idea is for secure operations to be routed so they never leave the chip and cannot be traced even if you scan the pins on the bus. I think in OMAP it is used for some cryptography operations.

On Reset the core starts in secure mode. It sets up the secure monitor (gateway between secure and non-secure world) and at this time FIQ can be setup to be routed to the monitor. I think it is the SCR.FIQ bit that may be set and then all FIQs ignore the value of CPSR.F and go to monitor mode. Check out the ARM ARM but if I remember correctly if this is happening there is no way for you to know from nonsecure OS code. Then the monitor will reset the Normal world registers and doing an exception return with PC set to the reset exception vector.

The core will take an interrupt to monitor mode, do its thing and return.

Sorry I can't answer you in the comments, I don't have enough reputation, you could always fix that ;), but I hope you see this

Upvotes: 1

paxdiablo
paxdiablo

Reputation: 882596

Other than enabling or disabling the IRQ/FIQ while you're in supervisor mode, there's no special setup you should have to do on the ARM to use it, unless the system (that the ARM chip is running in) has disabled it in hardware (based on your comment, this is not the case since you're seeing the FIQ input pin driven correctly).

For those unaware of the acronyms, FIQ is simply the last interrupt vector in the list which means it's not limited to a branch instruction as the other interrupts are. That means it can execute faster than the other IRQ handlers.

Normal IRQs are limited to a branch instruction since they have to ensure their code fits into a single word. FIQ, because it won't overwrite any other IRQ vectors, can just run the code directly without a branch instruction (hence the "fast").

The FIQ input line is just a way for external elements to kick the ARM chip into FIQ mode and start executing the correct exception. There's nothing on the ARM itself which prevents that from happening except the CPSR.

To enable FIQ in supervisor mode:

MRS r1, cpsr         ; get the cpsr.
BIC r1, r1, #0x40    ; enable FIQ (ORR to disable).
MSR cpsr_c, r1       ; copy it back, control field bit update.

A similar thing can be done for normal IRQs, but using #0x80 instead of #0x40.

Upvotes: 8

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