CODEWITHSUNDEEP
assemblyarm
user34537
user34537

Reputation:

ARM carry flag on EOR/XOR and AND

I was looking up some ARM assembly and i notice EOR/XOR and AND all set the C and O flag. How does that work? Are they always cleared? what conditions are they set?

Upvotes: 2

Views: 6088

Answers (4)

old_timer
old_timer

Reputation: 71606

If you decide to continue with ARM assembler you need a copy of the ARM ARM, which is the ARM Architecture Reference Manual. There are many versions and each have their own "features". I recommend collecting as many as you can but thats another story. There are a number of ways to get an electronic copy for free. Either way:

AND you need the S bit set which for ARM means use ANDS instead of AND. For thumb mode you are always using ANDS but gas for example refuses to accept ANDS in thumb mode (but always disassembles it as an ands).

If S==1 and Rd == R15 then 
  CPSR=SPSR
else if S==1
  N Flag = Rd[31]
  Z Flag = if Rd == 0 then 1 else 0
  C Flag = shifter_carry_out
  V flag = unaffected

EOR is the same as AND when it comes to the flags

Upvotes: 5

Stephen Canon
Stephen Canon

Reputation: 106317

As other posters noted, the C flag is updated based on a shift that is optionally applied to one of the source registers before the operation.

The V (overflow) flag is unaffected by these instructions.

The Z flag is set if the result is exactly zero, and the N flag is set if the result is negative when viewed as a twos-complement integer (i.e. the high order bit is a one).

Upvotes: 4

moonshadow
moonshadow

Reputation: 89175

Recall that you can arbitrarily shift the result following the operation. The carry flag is set based on the carry out from the barrel shifter. The overflow flag is never affected.

Upvotes: 2

paxdiablo
paxdiablo

Reputation: 882656

I don't believe the normal AND/EOR set the carry and overflow flags at all. The ANDS and EORS variants (AND/EOR with set) can set carry but only if the right hand side is a shifted operand. Neither of these affect the overflow flag at all.

For example,

ANDS R0,R1,R2, LSR #1

will set carry depending on b0 of R2. If the bit was 1 (i.e., R2 was odd), carry will be set.

See here for the gory details (chapter 3, the instruction set).

Upvotes: 6

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