CODEWITHSUNDEEP
makefilegnu-make
Pierre
Pierre

Reputation: 35306

Makefile rules: how should I specify a dependency with a modified target name?

I need to write a rule for the following pattern:

SAMPLE1.tsv : SAMPLE1_result23_R1.txt  SAMPLE1_result23_R2.txt
       (do something)

SAMPLE2.tsv : SAMPLE2_result54_R1.txt  SAMPLE2_result54_R2.txt
       (do something)
(...)

I tried something like:

%.tsv: $(wildcard %_*_R1.txt) $(wildcard %_*_R2.txt)
       (do something)

but that does not work. How should I write this kind of rule ?

Upvotes: 1

Views: 64

Answers (1)

tripleee
tripleee

Reputation: 189936

You cannot refer to % inside Makefile functions. You have to declare the dependencies separately, or use recursive Make, or generate the Makefile, or make do with less precise dependency declarations.

A simple refactoring of the dependencies is probably the easiest:

SAMPLE1.tsv: $(wildcard SAMPLE1_*_R1.txt) $(wildcard SAMPLE1_*_R2.txt)
SAMPLE2.tsv: $(wildcard SAMPLE2_*_R1.txt) $(wildcard SAMPLE2_*_R2.txt)
%.tsv:
        (do something with $^)

... where $^ will expand to the full list of dependencies.

I suppose you could refactor even further to do a foreach loop over SAMPLE1 and SAMPLE2 but if the dependencies are this simple (and fairly stable, so you don't have to edit the repetitive parts all the time), it's not worth the hassle.

Upvotes: 1

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