CODEWITHSUNDEEP
verilog
Eric
Eric

Reputation: 97631

Can I give part selects meaningful names in verilog?

Say I have an 8-bit flags register:

reg [7:0] flags;

While in my code I could refer to parts of it as flags[0], flags[3], flags[7:4] etc, I'd prefer to be able to do something along the lines of flags.Z, flags.C, flags.STATE.

Currently, I've found that this comes close:

`define Z [0]
`define N [1]
`define C [2]
`define V [3]
`define STATE [7:4]
reg [7:0] flags;

Which means I can both assign and evaluate flags`Z, flags`C, and flags`STATE.

However, polluting the global namespace with single-letter defines seems like a bad idea, particularly since notflags`N would be accepted by the compiler. Is this acceptable none-the-less?

Is there some easier way of doing this? I know SystemVerilog has structs, but I'm restricted to verilog 2001.

Upvotes: 3

Views: 380

Answers (2)

toolic
toolic

Reputation: 62154

I agree that you should avoid global define. I would just use a separate reg for each field, then assemble them as a wire:

reg Z, N, C, V;
reg [3:0] STATE;
wire [7:0] flags = {STATE, V, C, N, Z};

You can only assign to each reg, but you could use either the reg or the wire for eval.

Upvotes: 3

dwikle
dwikle

Reputation: 6978

Good question. As far as I know, there is nothing in Verilog-2001 that will help too much. Maybe someone else will have a better answer.

I can understand what you're trying to get to with the `defines, but I would think it would be less error-prone to use parameters. Then you don't have to worry about polluting the namespace as well. Of course, this really works best (in terms of readability) for single bit fields.

e.g.

localparam Z = 0;
localparam N = 1;
localparam C = 2;
localparam V = 3;
localparam STATE_MSB = 7;
localparam STATE_LSB = 4;

... flags[Z] ...
... flags[STATE_MSB:STATE_LSB] ...

You might also want to consider what you could do with functions.

Upvotes: 3

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