Makefile isn't rebuilding dependencies?

Question

Fair warning: I'm something of a newb at using makefiles, so this may be something obvious. What I'm trying to do is to use make to run a third-party code generation tool when and only when the source files for that generation tool (call them .abc files) change. I referenced the example at http://www.cmcrossroads.com/ask-mr-make/6795-rebuilding-when-a-files-checksum-changes which shows how to build MD5s, and I tweaked the idea a bit:

File: abc.mk

target = all
files    := $(wildcard Abc/*.abc)
bltfiles := $files $(addsuffix .built,$files)

all: $bltfiles

%.built: %.abc %.abc.md5
    @echo "Building $*"
    @ #Command that generates code from a .abc file
    @touch $@

%.md5: FORCE
    @echo "Checking $* for changes..."
    @ #Command to update the .md5 file, if the sum of the .abc file is different

FORCE:

What I'm intending to happen is for each .abc file to have two auxilary files: .abc.built & .abc.md5 . The .built file is just a dummy target & timestamp for the last time it was built, as the code produced by the generation tool cannot be readily defined as a target. The .md5 file contains a hash of the last known content of the .abc file. It should only be updated when the hash of the file changes.

However, the .built file is only created if it doesn't exist. The .md5 rule never runs at all, and the .built rule doesn't re-build even if the .abc file has a newer timestamp. Am I doing something wrong?

Update: For posterity, here's the version I got to work:

File: abc.mk

# Call this makefile as: make all --file=abc.mk

# Default Target
target = all

COMP_ABC_FILES := $(wildcard Abc/*.abc)
COMP_BLT_FILES := $(COMP_ABC_FILES) $(addsuffix .built, $(COMP_ABC_FILES) )

# This line is needed to keep make from deleting intermediary output files:
.SECONDARY: 

# Targets:
.PHONY: all
all: $(COMP_BLT_FILES)

Abc/%.abc.built: Abc/%.abc Abc/%.abc.md5
    @echo "Building $*"
    @ #Command that generates code from a .abc file
    @touch $@

%.md5: FORCE
    @echo "Checking $* for changes..."
    @$(if $(filter-out $(shell cat $@ 2>/dev/null),$(shell md5sum $*)),md5sum $* > $@)

# Empty rule to force re-build of files:
FORCE:

clean:
    @echo "Cleaning .built & .md5 files..."
    @rm Abc/*.built
    @rm Abc/*.md5

Answer 1

Fixing your makefile in three places:

target = all
files    := $(wildcard Abc/*.abc)
bltfiles := $(files) $(patsubst %.abc,%.built,$(files))

all: $(bltfiles)

#Abc/%.abc.built: Abc/%.abc Abc/%.abc.md5
%.built: %.abc %.abc.md5
    @echo "Building $*"
    @ #Command that generates code from a .abc file
    @touch $@

%.md5: FORCE
    @echo "Checking $* for changes..."
    @ #Command to update the .md5 file, if the sum of the .abc file is different

FORCE:

Note the changes:

1. bltfiles := $(files) $(patsubst %.abc,%.built,$(files))

   Results in "Abc/a.built Abc/b.built" instead of "Abc/a.abc.built Abc/b.abc.built", which was required given how the rule for %.built was defined

2. all: $(bltfiles)

   As above, with $(files), '$bltfiles' needed to be $(bltfiles), since otherwise make will interpret this as $(f)iles and $(b)ltfiles instead.

Tip: Having an editor with syntax highlighting for makefiles is nice here

---

DEMO

mkdir -pv Abc; touch Abc/{a,b,c,d,e,f,g}.abc
make -Bs -f abc.mk

output like

Checking Abc/e.abc for changes...
Building Abc/e
Checking Abc/g.abc for changes...
Building Abc/g
Checking Abc/b.abc for changes...
Building Abc/b
Checking Abc/f.abc for changes...
Building Abc/f
Checking Abc/a.abc for changes...
Building Abc/a
Checking Abc/c.abc for changes...
Building Abc/c
Checking Abc/d.abc for changes...
Building Abc/d

Answer 2

As sehe fixed but didn't explain: Makefile syntax isn't the same as shell syntax. By default (for reasons lost to history) make variables are only one character long. If you want a longer variable name, you have to put it in parenthesis so it parses correctly. Writing $files, for example, actually expands the string "iles" because make parses and expands only the value of the "f" variable (which is empty).

Yes, it's weird. But it's the way make works. Always put your variables in parentheses.