CODEWITHSUNDEEP
operating-systemx86kernelinterrupt
Bruce
Bruce

Reputation: 35255

Stack for iret and int instruction

An interrupt causes the CPU to save the EFLAGS, CS and IP registers onto the "stack" and the iret instruction pops them off it. Where is this stack located? How does the CPU know about it (I assume some register somewhere)? I want the dirty details. I am looking at Unix based systems. Say Linux.

Upvotes: 1

Views: 2925

Answers (3)

Mohanraj
Mohanraj

Reputation: 4200

SS:(E)SP - SS(Stack segment) SS is the 16 bit register available inside the CPU, and (E)SP is 16(in real mode), 32, 64 bit size in protected mode.

  1. At initial BIOS POST, the valid SS:(E)SP is set by BIOS.
  2. And BIOS gives control to MBR, then in your MBR bootloader code you can reset and set the valid SS:(E)SP valus.
  3. In protected mode, we need to set valid GDT values for add segments CS, DS, SS, then the loading the appropriate values to segments are the responsibity of CPU, for this OS should co-ordinate.

Upvotes: 1

srking
srking

Reputation: 4732

First, check out the Intel manuals for all the specifics: http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html

As to your questions:

Where is the stack located?

On an interrupt, an x86 core loads the stack pointer from the Task-state Segment (TSS). The IDT specifies which TSS to use via a task selector field. In 32-bit mode, the TSS provides 4 stack pointers, one per each protection level. Since the protection level is usually just 0 or 3, only two stacks are relevant. In 64-bit mode, the interrupt descriptor entry can optionally specify an index 0-7 of which stack pointer to use within a given 64-bit TSS. Due to reentrancy problems though, this 64-bit stack selection mechanism is mostly broken and OS's resort to software switching. Check out the x86 Programmer Reference Volume 3, Figure 7-2.

If the interrupt moves the core to a higher privilege level (numerically lower CPL), then the core pushes the interrupt stack frame onto this new stack, not the current stack of the interrupted process. If the privilege level stays the same, then the core just pushes the interrupt stack frame in place on the current stack.

How does the CPU know about it?

The interrupt descriptor table (IDT) provides a descriptor per each interrupt vector, 0-255. The descriptor entry tells the core which TSS (i.e. stack) to use, whether user-mode can call through the vector, whether interrupt are disable on ISR entry, etc. See PRM Volume 3, chapter 6. So, all interrupt processing is really anchored by the information in the IDT.

Upvotes: 3

Alexey Frunze
Alexey Frunze

Reputation: 62048

An interrupt does not cause the OS to save EFLAGS, CS and IP. The CPU does this itself, without the OS.

The very first stack is set up by the very first code executed on the CPU following the reset. Typically it's the ROM BIOS code to do it first. It sets the SS and SP registers to indicate the stack location. Then the stack can be, and usually is, changed/moved by the bootloader and then it may be moved again by the kernel.

Wherever the aforementioned pieces of code want to locate the stack, they can do as long as there's readable and writable memory of sufficient size.

Upvotes: 2

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