CODEWITHSUNDEEP
assemblymips
newprint
newprint

Reputation: 7136

dealing with immediate offsets when moving instruction to fill the branch delay slot in MIPS

Some of the MIPS instructions have immediate offsets. For example, while moving lw command to fill the branch delay slot below the beq, its immediate offset changes from 100 to 96. 

PC     Loop: lw $2, 100($3)
PC+4         addi $3, $3, 4
PC+8         beq  $3, $4, Loop

transformed into 

PC   Loop: addi $3, $3, 4
PC+4       beq $3, $4, Loop
PC+8       lw $2, 96($3) # branch delay slot

Is it because PC is always PC+4, so it goes as 100 - 8 + 4 = 96 ? What happens if instruction is moving up? For example,

PC       Loop: xxxxxxxxxxxxx
PC+4           addi $5, 4($5)

Will this be correct? 

PC       Loop: addi $5, 4($5)
PC+4           xxxxxxxxxxxxx

Upvotes: 1

Views: 536

Answers (1)

ninjalj
ninjalj

Reputation: 43688

The change in the immediate has nothing to do with the PC. 

Loop: lw $2, 100($3)
      addi $3, $3, 4
      beq  $3, $4, Loop

In the original you are loading from address ($3 + 100), then adding 4 to $3.

Loop: addi $3, $3, 4
      beq $3, $4, Loop
      lw $2, 96($3) # branch delay slot

In the transformed one, you are adding 4 to $3, then loading from address ($3 + 96) = (original_$3 + 4 + 96) = (original_$3 + 100). It's the reordering between lw and addi which affects the immediate (addi cannot be moved to the delay slot because the branch depends on the new value of $3).

Upvotes: 2

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