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linuxlinux-kernelarmfault
shunty
shunty

Reputation: 375

Kernel Oops page fault error codes for ARM

What does error code after Oops give information about the panic in arm ex. Oops: 17 [#1] PREEMPT SMP what 17 give information in this case. In x86 it represents -

But i am not able to find any information in arm.

Thanks Shunty

Upvotes: 5

Views: 30716

Answers (2)

auselen
auselen

Reputation: 28087

What you printed above as description of bits is page fault descriptions, not Oops faults.

See Linux's oops-tracing for more information on looking for Linux crash analysis.

Below is how your Oops: 17 [#1] PREEMPT SMP arch/arm/kernel/traps.c:

    #define S_PREEMPT " PREEMPT"
    ...
    #define S_SMP " SMP"
    ...
    printk(KERN_EMERG "Internal error: %s: %x [#%d]" S_PREEMPT S_SMP S_ISA "\n", str, err, ++die_counter);

Page faults doesn't need to crash the kernel, as well as not all kernel crashes are page faults. So there is a high chance Oops: 17 is not related to page faults at all. (and as a bonus my wild guess is it is about scheduling / just sounds familiar to me.)

Upvotes: 2

kaiwan
kaiwan

Reputation: 2144

Looks like you're asking about the ARM Fault Status Register (FSR) bits. I looked up the kernel code (arch/arm/mm/fault.c) and found that this is what is actually passed as a parameter to the Oops code:

    static void
    __do_kernel_fault(struct mm_struct *mm, unsigned long addr, unsigned int fsr,
              struct pt_regs *regs)
    {
    [...]
        pr_alert("Unable to handle kernel %s at virtual address %08lx\n",
             (addr < PAGE_SIZE) ? "NULL pointer dereference" :
             "paging request", addr);

        show_pte(mm, addr);
        die("Oops", regs, **fsr**);
   [...]
   }

So, anyway, this I traced to the FSR register on the ARM(v4 and above?) MMU:

Source: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0438d/BABFFDFD.html 

...
    [3:0]   FS[3:0] 
    Fault Status bits. This field indicates the type of exception generated. Any encoding not listed is reserved:
    b00001
       Alignment fault.
    b00100
       Instruction cache maintenance fault[a].
    b01100
       Synchronous external abort on translation table walk, 1st level.
    b01110
       Synchronous external abort on translation table walk, 2nd level.
    b11100
       Synchronous parity error on translation table walk, 1st level.
    b11110
       Synchronous parity error on translation table walk, 2nd level.
    b00101
       Translation fault, 1st level.
    b00111
       Translation fault, 2nd level.
    b00011
       Access flag fault, 1st level.
    b00110
       Access flag fault, 2nd level.
    b01001
       Domain fault, 1st level.
    b01011
       Domain fault, 2nd level.
    b01101
       Permission fault, 1st level.
    b01111
       Permission fault, 2nd level.
    b00010
       Debug event.
    b01000
       Synchronous external abort, non-translation.
    b11001
       Synchronous parity error on memory access.
    b10110
       Asynchronous external abort.
    b11000
       Asynchronous parity error on memory access.

...

Disclaimer: I don't know whether this info is still relevant; the doc states it's for the ARM Cortex A15 and the page is marked as Superseded.

Could see this page also: ARM926EJ-S Fault address and fault status registers

Upvotes: 1

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