CODEWITHSUNDEEP
cmakefile
Travis Griggs
Travis Griggs

Reputation: 22252

How to build multiple targets from one makefile

I'm trying to parameterize my makefile targets. Currently, it has a 

TARGET = main

declaration near the top. It derives the SRC list from that as well as does lots of other things.

I've changed my C code though, so that I have multiple different top level .c files to basically get variant builds. So what I want to be able to do is basically do

make target1

or

make target2

And vary what TARGET is set to in the makefile. I'm confused how to accomplish this. I thought I might add something like

target1: all
    TARGET=target1

This didn't seem to work too well at all though. Is there a general pattern for how one does this?

Upvotes: 12

Views: 68946

Answers (4)

tyskstil
tyskstil

Reputation: 88

Adding to Eric Melskis comment, if you wanted also have your 'make all' functionality make both programs, then perhaps this would be a good substitute:

target1_SRC=123 456
target2_SRC=abc def

all: target1 target2

target1: TARGET=target1
target2: TARGET=target2

target1: ; @echo $($(TARGET)_SRC)
target2: ; @echo $($(TARGET)_SRC)

Here I also added the default rule to have both targets made by default.

Upvotes: 0

MarzVIX
MarzVIX

Reputation: 29

Well... Using pmake we can do this: (If use gmake we can replace $(.THINGS) for equivalanet $@ $< and so...

.PHONY: clean run

PROGRAMS = progrname_one progrname_two... and so

all: $(PROGRAMS)

$(PROGRAMS): $(PROGRAM=$(.TARGET))

CC = clang -I.

CFLAGS = -O0 -g -std=gnu11 

OBJS = 

LIBS = 

CPATH = .

$(PROGRAM): $(PROGRAM).c $(OBJS)
    $(CC) $(CFLAGS) -o $(.TARGET) $(.IMPSRC) $(OBJS) $(LIBS) 

$(PROGRAM).o: $(PROGRAM).c

clean:
    rm -f *~
    rm -f *.core
    rm -f $(PROGRAMS) $(PROGRAMS).o

run:
    ./$(PROGRAM)

dbg:
    lldb ./$(PROGRAM)

Upvotes: 3

John Marshall
John Marshall

Reputation: 7005

I would suggest simply spelling out your targets as separate targets in the makefile:

all: target1 target2

OTHER_OBJS = misca.o miscb.o miscc.o

target1: target1.o $(OTHER_OBJS)

target2: target2.o $(OTHER_OBJS)

Then make, make target1, make target2, and so on will all do what you want.

You say your makefile "derives the SRC list from [$(TARGET)]" in some presumably high-tech way, but it might be interesting to try explicitly listing the object files in a low-tech way instead, as above. Using different make targets is arguably Make's general pattern for producing different results.

Upvotes: 21

Eric Melski
Eric Melski

Reputation: 16790

Parameterized variable names and target-specific variables may do what you want, as the value of a target-specific variable is normally "inherited" by the prereqs of that target (assuming you are using GNU make):

target1_SRC=123 456
target2_SRC=abc def

target1: TARGET=target1
target2: TARGET=target2

target1: all
target2: all

all: ; @echo $($(TARGET)_SRC)

Then you can run make target1 or make target2, for example:

$ make target1
123 456
$ make target2
abc def

Upvotes: 12

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