CODEWITHSUNDEEP
gccmakefiledependencies
Jack Kelly
Jack Kelly

Reputation: 2574

Makefile with multiple targets and automatic dependency generation using g++ -MMD

Another question on SO describes a wonderfully elegant makefile for a single target:

CXX = g++                     # compiler
CXXFLAGS = -g -Wall -MMD      # compiler flags
OBJECTS = x.o y.o z.o         # object files forming executable
DEPENDS = ${OBJECTS:.o=.d}    # substitutes ".o" with ".d"
EXEC = a.out                  # executable name

${EXEC} : ${OBJECTS}          # link step
    ${CXX} ${OBJECTS} -o ${EXEC}

-include ${DEPENDS}           # copies files x.d, y.d, z.d (if they exist)

My question is: how can we adapt this for multiple targets?

Upvotes: 0

Views: 1038

Answers (2)

Beta
Beta

Reputation: 99144

Your solution looks good, but if there are many targets this is a tiny bit easier to scale:

EXECS = exec_x exec_y

exec_x: a.o b.o c.o
exec_y: d.o e.o f.o

$(EXECS):
    ${LINK}

Upvotes: 1

Jack Kelly
Jack Kelly

Reputation: 2574

I've hacked together a solution which appears to work but I'd love to know if this is the appropriate technique.

CXX = g++                     # compiler
CXXFLAGS = -g -Wall -MMD      # compiler flags
LINK = ${CXX} $^ -o $@        # link step

exec_x: a.o b.o c.o
    ${LINK}

exec_y: d.o e.o f.o
    ${LINK}

-include *.d

Upvotes: 0

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