CODEWITHSUNDEEP
typesintegerverilog
Hardell
Hardell

Reputation: 741

Cannot work with integers in Verilog

I've been trying to figure out why I'm getting "invalid module instantiation" when using:

integer counter = 0; 
counter = 1; // <-- getting the error here

I'm getting the same error when trying to use reg[7:0] instead of integer.

Does anybody have any idea why?

Upvotes: 2

Views: 528

Answers (1)

user405725
user405725

Reputation:

The assignment without a context is pretty useless and doesn't mean anything, thus the error. Assignment would have been valid within a block with a sensitivity list, or as part of continuous assignment, or inside a simulation block like "initial".

Upvotes: 4

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