CODEWITHSUNDEEP
verilog
user2011976
user2011976

Reputation: 11

Verilog calling a multiplexer module in another module

I am trying to use Verilog to build a module which near the end calls a multiplexer (already designed and in the file). However, when I call the multiplexer and assign its inputs, I get an error saying:

    Syntax error near "[".

The line it references is this:

    .MUX_in[0](inv_ymux),

I'm trying to call the first bit of my 4 bit MUX_in (which is specified in my multiplexer module). Am I doing this correctly? how should I go about assigning it?

    module multiplexer(MUX_in, S_in, MUX_out);
    input [3:0] MUX_in;
    input [1:0] S_in;
    output MUX_out;

    reg MUX_out;

    always @ (MUX_in or S_in)begin
        case(S_in)
            2'b00: MUX_out = MUX_in[0];
            2'b01: MUX_out = MUX_in[1];
            2'b10: MUX_out = MUX_in[2];
            2'b11: MUX_out = MUX_in[3];
        endcase
    end
    endmodule

Above is the module for the multiplexer.

Upvotes: 1

Views: 2489

Answers (1)

toolic
toolic

Reputation: 62037

One way to do it is to concatenate other signals in your port connections. The following connects inv_ymux to MUX_in[0]:

mux i0 (
    .MUX_in ({3'b000, inv_ymux}),
    // other port connections
);

Upvotes: 2

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