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loopsverilog
Verilogger
Verilogger

Reputation: 5

Implementing a closed loop in verilog

I'm trying to implement a loop without using loop instructions in verilog so i made a counter module and the simulation went perfectly but when i tried to implement it on the FPGA i got a lot of errors in the mapping , like this one 

ERROR:MapLib:979 - LUT4 symbol
"Inst_Count/Mcompar_GND_1105_o_xcount[7]_LessThan_25_o_lut<0>" (output
signal=Inst_Count/Mcompar_GND_1105_o_xcount[7]_LessThan_25_o_lut<0>) has
input signal "Inst_Count/Madd_x[9]_GND_1105_o_add_0_OUT_cy<0>" which will be
trimmed. See Section 5 of the Map Report File for details about why the input
signal will become undriven.

These errors only occurred when i replaced this module with the loop instruction module so does anyone no what's the problem with this one ?

Thanks for giving this your time :)

module average( input rst , output reg [7:0]
reg [7:0] count;
reg [7:0] prv_count;

reg clk;

initial
begin

count = 8'd0;

end

always @ (posedge rst)
begin

clk = 1'b0;

end

always @ (clk)
begin

prv_count = count ;
count = prv_count + 1'b1;

end

always @ (count)
begin

if (count == 8'd255)
G_count= count;
else
begin

clk = ~clk;
G_count= count;

end

end
endmodule

Upvotes: 0

Views: 655

Answers (1)

user405725
user405725

Reputation:

Oh, this is just plain wrong. I don't really think anybody can help here without giving you a lecture on Verilog, but... some things that are noticeable right away are:

  1. You have an obvious syntax error in your module parameter list where you do not close it (i.e. ) went missing).
  2. Clock should be an input to your module. Even if you depend on reset input only and use a register as a "clock", it won't work (logically and you have combinatorial loop that must be broken or else...).
  3. Do not use initial block in the code that should be synthesizable.
  4. prv_count is useless.
  5. No need to manually take care of the overflow (check for 255? 8'd255 is exactly 8'b11111111 and it resets to 0 if you add 1'b1, etc).

And tons of other things, which raise the obvious question — have you tried reading some books on Verilog, preferably those covering synthesizable part of the language? :) Anyhow, what you are trying to do (as far as I can understand) would probably look something like this:

module average(input clk, input rst, output reg [7:0] overflow_count);
   reg [7:0] count;

   always @(posedge clk or negedge rst) begin
      if (~rst) begin
         count <= 8'b0;
         overflow_count <= 8'b0;
      end else begin
         count <= (count + 1'b1);
         if (count == 8'b0)
           overflow_count <= (overflow_count + 1'b1);
      end
   end
endmodule

Hope it helps and really suggest you take a look at some good books on HDL.

Upvotes: 2

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