CODEWITHSUNDEEP
makefile
jayant
jayant

Reputation: 2389

Makefile as a dependency for a make target

Is it ever a bad idea to include a Makefile as a dependency for a make target?

Eg.

hello.o: hello.cxx Makefile
    $(CXX) -c  $(CFLAGS) $< -o $@

That way anytime the Makefile is modified the target is recompiled.

Upvotes: 1

Views: 294

Answers (2)

Tuxdude
Tuxdude

Reputation: 49473

I believe what you're trying to do is run clean (or other equivalent target) whenever the Makefile gets modified.

This can be achieved so. (I've been using this recipe in couple of my C/C++ projects).

CLEANUP_TRIGGER := .makefile
BASE_MAKEFILE := $(firstword $(MAKEFILE_LIST))
FINAL_TARGET := hello.o

all: $(CLEANUP_TRIGGER) $(FINAL_TARGET)

hello.o : hello.c
    $(CXX) -c $(CFLAGS) $< -o $@

$(CLEANUP_TRIGGER): $(BASE_MAKEFILE)
    if [ -f $(CLEANUP_TRIGGER) ]; then $(MAKE) clean; fi
    touch $@

clean:
    rm -rf *.o
    rm -f $(CLEANUP_TRIGGER)

.PHONY: all clean

The essence is to make sure CLEANUP_TRIGGER is part of the rules which get invoked commonly, run make clean whenever Makefile is newer than CLEANUP_TRIGGER.

Upvotes: 0

Sagar Sakre
Sagar Sakre

Reputation: 2426

No its not a bad idea. Conventionally we never do that but if you have makefile calling other makefile then including it would be a great idea though.

Upvotes: 2

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