CODEWITHSUNDEEP
vhdlmodelsim
Salahuddin
Salahuddin

Reputation: 1719

Can't perform logic operations on unsigned in VHDL?

I've a problem in performing logic operations on unsigned:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;    
with sel select
s_1<=a+b when "000",
a+((not b)+1) when "001",
s_2 when "010",
s_3 when "011",
s_4 when "100",
(others=>'0') when others;

Here there's an error:

No feasible entries for prefix operator "not"

s_1,a,b,s_2,s_3,s_4 are all of type unsigned(31 downto 0).

I found a code that converts std_logic_vector to unsigned to enable logic operations on std_logic_vector if it can't be done on unsigned but this code was using numeric_std.all which when used I think it conflicted with std_logic_arith and made the datatypes of unsigned unknown.

Now I don't know how to perform logic operations on unsigned and I don't know how to convert std_logic_vector to unsigned. Can someone help me?

Upvotes: 0

Views: 1951

Answers (2)

Martin Thompson
Martin Thompson

Reputation: 16802

A horrible workround would be to xor b with a vector of all ones...

Upvotes: 0

user1818839
user1818839

Reputation:

You are using a non-standard library, use ieee.std_logic_arith.all; which apparently does not implement the "not" operator.

use ieee.numeric_std.all; in its place should resolve the problem.

Upvotes: 1

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