CODEWITHSUNDEEP
makefiletarget
Jeff Goguen
Jeff Goguen

Reputation: 31

Is there a way to reference a target specific variable in a Makefile's Rule?

1 target foo : src = foo.c
2 target foo : obj = foo.o
3 target bar : src = bar.c
4 target bar : obj = bar.o

5 foo bar: obj   # problem - not recognizing obj!
6    @echo link ${bin}     
7    @gcc command to link ${obj}

8 foo.o bar.o
9    @echo compile ${src}
10   @gcc command to compile ${src}

So, target specific variable are great for the target recipe as used in lines 6,7,9 & 10. However, is there a way I can reference the target specific variable "obj" in the target rule itself as i have in line 5? I'm thinking there is, but I need some voodoo symbol to reference it. Can't believe I couldn't find this answer anywhere. Thanks in advance!

Upvotes: 2

Views: 913

Answers (2)

Eldar Abusalimov
Eldar Abusalimov

Reputation: 25533

Use secondary expansion:

.SECONDEXPANSION:

foo bar: $$(obj)
    ...

Upvotes: 4

Maxim Egorushkin
Maxim Egorushkin

Reputation: 136515

I think you want prerequisites, rather than target specific variables:

foo : foo.o
bar : bar.o

foo bar :
    gcc -o $@ $^ ${LDFLAGS } ${LDLIBS}

# use the default rule for .c to .o

Note that $^ expands to the list of all prerequisites.

Upvotes: 2

Related Questions