CODEWITHSUNDEEP
vhdlxilinxhdl
Wazani
Wazani

Reputation: 911

xilinx VHDL error 827 : Signal <name> cannot be synthesized

I am beginner in VHDL programming and I am trying to synthesize the following vhdl code (software denouncing for a push button) using ISE project navigator 13.1 

entity PBdebouncer is
Port ( PB : in  STD_LOGIC;
       CLK : in  STD_LOGIC;
       reset : in  STD_LOGIC;
       PBdebounced : out  STD_LOGIC);
end PBdebouncer;

architecture Behavioral of PBdebouncer is

begin

    p1: process(CLK , PB , reset)
        variable enable,count : integer range 0 to 100000 := 0;
    begin
        if(reset = '1') then
            count := 0;
            enable :=0;
        elsif(CLK' event and CLK = '1' ) then
            if (enable = 1) then
                count := count + 1;
            end if;

            if(count = 99999 ) then 
                if(PB = '0') then
                    PBdebounced <= '0';
                else
                    PBdebounced <= '0';
                end if;

                count := 0;
                enable := 0;
            end if;

            count := count;

        else
            enable := 1;
        end if;

    end process;
end Behavioral;

but unfortunately I am bumped with the following error:

ERROR:Xst:827 - ".../digital lab II 110/PBdebouncer/PBdebouncer.vhd" line 43: Signal enable cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.

So could you please explain this error for me ?

Upvotes: 1

Views: 4641

Answers (3)

user2099996
user2099996

Reputation: 134

Just a small advice: Avoid variables as beginner. They seem to work like in a software program, but they map sometimes to nasty things in hardware.

Upvotes: 2

sonicwave
sonicwave

Reputation: 6092

The cause of the problem seems to have been identified by Brians answer - but I'll just add a tip for these cases:

In Xilinx ISE you can view a number of language templates (select Edit -> Language templates), which can help you when implementing various styles of flip-flops (synchronous / asynchronous resets, rising / falling edge triggered and so on) and other constructs.

These can be really helpful - especially when getting error-messages like this, which are typically due to syntactically correct VHDL code that describes hardware that can't be synthesized in the selected device.

Upvotes: 1

user1818839
user1818839

Reputation:

Try it without the space between Clk' and event...

A few other questions :
why does "enable" have a range of 0 to 100000 when you only use two of those values? why not just use a boolean or std_logic?
is "pbdebounced" ever supposed to be set to anything other than '0'?
why the parentheses around the boolean expressions?
why is PB in the sensitivity list?
did it work as expected in simulation?

these will probably do for now...

EDIT : the bad formatting hid the problem: 

begin
   if reset = '1' then
      count := 0;
      enable :=0;
   elsif rising_edge(clk) then
      if enable = 1 then 
         count := count + 1; 
      end if;
      if count = 99999 then 
         -- do stuff
      end if;
      count:= count;
-- else   
-- enable := 1;
-- THE TWO LINES ABOVE are the problem
-- They are outside both the CLK and RESET clauses.
   end if;
end process;

Upvotes: 4

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