CODEWITHSUNDEEP
vhdlboolean-logicbitvector
user2114571
user2114571

Reputation: 21

VHDL: How to check selected bits of a vector

I'm wondering if there is a way to check only the bits I'm interested in of an std logic vector in VHDL. My newest attempt looks like this:

IF (vectorname = "1-00") THEN

action

END IF;

I am here only interested to check the bits 3, 1 and 0 of the vector. Bit 2 is in this case irrelevant. I thought a - would work since it's "don't care", but it doesn't.

Any ways to do this simply? I know it's possible with STD_MATCH, but I want to take a different approach.

Upvotes: 2

Views: 19001

Answers (2)

danv
danv

Reputation: 31

First way (also answered by vermaete as a comment):

IF vectorname(3) = '1' AND vectorname(1 DOWNTO 0) = "00" THEN
  action
END IF;

...the above works if it's inside a process. If not, use something like this:

my_output <= "11111111" WHEN vectorname(3) = '1' AND vectorname(1 DOWNTO 0) = "00" ELSE "00000000";

Second way:

SIGNAL bits_i_care_about : STD_LOGIC_VECTOR(2 DOWNTO 0);


bits_i_care_about <= vectorname(3) & vectorname(1 DOWNTO 0);

p_my_process : PROCESS(bits_i_care_about)
BEGIN
  IF bits_i_care_about = "100" THEN
    action
  END IF;
END PROCESS;

Upvotes: 0

Martin Thompson
Martin Thompson

Reputation: 16822

What's wrong with std_match? That's the "right" way to do it IMHO and I can't immediately think of a reason to "take a different approach"...

Upvotes: 1

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