CODEWITHSUNDEEP
arraysvhdl
wsmccusker
wsmccusker

Reputation: 2881

Array literals in VHDL

We have defined a vector as 

A: in std_logic_vector(7 downto 0);

when assigning a literal to this vector such as 

A <= {'1', '0', '0', '1'};

will this expession populate the vector positions of 7,6,5 & 4 or positions of 3,2,1 & 0

The idea is a vector of bits which we can sign extend to an 8 bit integer but it will only currently work if the latter is true.

Upvotes: 0

Views: 1134

Answers (4)

Martin Thompson
Martin Thompson

Reputation: 16792

If you want sign extension, use the appropriate type signed.

Then you can convert a proper number (like -1) to a vector of the appropriate width using the to_signed function, for example:

to_signed (-1, a'length)

Advantages to doing this over explicit bit setting are:

  • simpler code
  • everyone can read it and understand what you are doing (no comments necessary!)
  • when a changes length, it all (still) Just Works

Upvotes: 0

Voider
Voider

Reputation: 454

Invalid syntax here. If you want to keep the various bits as a list you can make the assignment:

A(3 downto 0) <= (3 => '1', 2=> '0', 1=> '0', 0=> '1') ;

Bonus sign extension:

A <= (2=> '0', 1=> '0', 0=> '1', others => '1') ;

Upvotes: 3

Charles Steinkuehler
Charles Steinkuehler

Reputation: 3365

Why are you using individual bits as a numeric constant? Is there some reason you're not doing something like:

A <= std_logic_vector(to_signed(-7,A'length));

You can get rid of the std_logic_vector cast if you A is a signed type to start with, and you can use unsigned types and conversion functions if you don't want sign extension.

Upvotes: 1

sonicwave
sonicwave

Reputation: 6092

I don't think this is legal - at least it isn't in Xilinx ISE.

The right way to do it would be to specify the part of A that you want to assign:

A(3 downto 0) <= "1001";

Upvotes: 1

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