CODEWITHSUNDEEP
vhdl
gccinac
gccinac

Reputation: 93

Detecting the rising edge of an std_logic signal in VHDL

I have a flip flop which uses as clk input a signal which comes from the processing of to other signals. That means, that I'm not using the clock of the system neither an input. Thus, when I do:

architecture sampler_a of sampler_e is
  signal S0_s   : std_logic := '0';  
begin
  -- In my block this is not only a not. I put this to simplify things.
  S0_s <= not(S0_i);                   
  S0_o <= S0_s;

  process(S0_i)
  begin
    --Also with rising edge does not work
    if (S0_s'event and S0_s= '1') then
        BitReady_o <= '1';
    end if;   
  end process;
end sampler_a;

BitReady does not change in the simulation (in modelsim). Is the use of std_logic incorrect here? Note that I don't want to generate a pulse that is a clock period's wide, because my circuit works in an asynchronous way.

Upvotes: 1

Views: 7071

Answers (1)

user1818839
user1818839

Reputation:

The process is only sensitive to S0_i, but only tests for events on S0_s (which are never in the same delta cycle as S0_i events). Thus the process can never do anything.

Change its sensitivity list to S0_s and if ought to work. However, as currently written, once BitReady_o becomes '1', there is no way to ever return it to '0'.

Upvotes: 2

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