CODEWITHSUNDEEP
functionverilogsystem-verilog
koudi sidi
koudi sidi

Reputation: 33

Unusual function declaration in Verilog

To try to understand, I looked for some code on the internet and found the following declaration of what I suppose to be functions, and that I don't understand at all.

sext #(.inwidth(1), .outwidth(32))  scc_sext_i0(
                  .i0(paw_0_i0_outport0[32]),
                  .o0(scc_sext_i0_o0));

combine2_wn #(.inwidth0(32), .inwidth1(32))  scc_combine2_wn_i0(
                  .i0(paw_0_i0_outport0[31 : 0]),
                  .i1(scc_sext_i0_o0),
                  .o0(scc_combine2_wn_i0_o0));


combine2_wn #(.inwidth0(32), .inwidth1(32))  scc_combine2_wn_i1(
                  .i0(scc_combine2_wn_i2_o0[31 : 0]),
                  .i1(scc_combine2_wn_i2_o0[63 : 32]),
                  .o0(scc_combine2_wn_i1_o0));

My questions are the following:

  1. Are these really functions mapping?
  2. If yes, they are not defined in any other lower level .v file (and no library is included either in the top-level file). So what is their use?
  3. What does # symbol mean?
  4. What does .inwidth(32) mean? input of 32 bits? (impossible to find on the internet...)
  5. If yes, the combine2_wn blocks should have only 2 inputs, why is there an output mapped each time?

More generally, are these any kind of concatenation functions?

Upvotes: 0

Views: 257

Answers (1)

toolic
toolic

Reputation: 61937

These are most likely module instantiations, not function calls.

You should have a module named sext and another named combine2_wn declared in files somewhere in your Verilog search path.

#() means you are assigning values to parameters inside the named modules.

There is a parameter named inwidth in the sext module. You are assigning it a value of 1.

There are plenty of references on the web. Look at the verilog wiki site.

Upvotes: 4

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