Reputation: 4794
I'm currently writing a makefile that is able to compile different targets (Like Debug, Development, Release). The linking and compiling rules look like that:
$(DEVELOPMENT_OUT): $(subst rep,development,$(OBJS))
g++ -o $(DEVELOPMENT_OUT) $(subst rep,development,$(OBJS))
obj/development/%.o: src/%.cpp
g++ -c -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -o "$@" "$<"
Now, I get this output:
make: *** No rule to make target 'obj/development/Main.o', needed by 'bin/Development.exe'. Stop.
But shouldn't the pattern rule apply for the Main.o?
I use GNU Make 3.82.90
of MinGW.
Upvotes: 0
Views: 227
Reputation: 100856
There's not enough information here to say why it doesn't work. If you're sure you have a file src/Main.cpp
then make should choose that rule. Is the cpp file a source file, or a generated file? If it's generated then maybe the real problem is lower down, where the generating happens. You can try using make -d
to see what make is doing and why it doesn't like this rule.
Upvotes: 1