CODEWITHSUNDEEP
vhdl
ted
ted

Reputation: 4975

VHDL read generic default value

I would like to know if there is a way to access an entities default generic values or an entities architectures constants during synthesis.

This is out of curiosity (and I want to implement something like that).

Possible Usecases

1) generating Testbench for the default entity:

entity testme is
    generic(outputs:integer:=4);
    ports(output:out bit_vector(0 to outputs);
end entity;

in the testbench i need to generate a signal whcih can be connected to output, without knowing the generics value there is no way of doing so.

2) I would like to know the actual size I use when instantiating Blockram. On FPGAs there is Blockram, fixed chunks of ram one can use, if one needs more ram than is available in one block multiple blocks are combined. Varying with the technology the size of the available blockrams can change. Thus I write an entity with two generic parameters memory and technology that implements my memory with the least Blockrams possible. This might lead to the Memory being larger than requested. If I now have another entity that needs the size of the memory to fully utilitize it (i.e. circular buffer controller), I have to supply it the actual size of the memory allocated.

Upvotes: 2

Views: 1537

Answers (2)

baldyHDL
baldyHDL

Reputation: 1387

you can use unconstraint types, e.g.:

entity example
port(
    i: std_logic_vector;
    o: std_logic_vector
);

in the testbench you add defined vectors e.g.:

....
signal i,o: std_logic_vector(10 downto 0);

begin
   uut: example
   port map(
      i => i,
      o => o
   );

Upvotes: 0

Martin Thompson
Martin Thompson

Reputation: 16792

You have to push these things downwards from the top (ie from the testbench). It is not possible to inspect a lower-level block (although I guess you could bring a signal out and back up to the top!)

Upvotes: 0

Related Questions