Reputation: 5125
I wrote the following makefile using automatic variables($@,$^
) and pattern(%
),but it can't work with gnu make:
TARGET = edit
SRCS = $(wildcard *.c)
OBJS = $(SRCS:%.c=%.o)
$(TARGET) : $(OBJS)
gcc $^ -o $(TARGET)
%.o : %.c
gcc $< -c $@
I have foo.c ,bar.c in the working directory. The error is :
gcc foo.c -c foo.o
gcc: foo.o: No such file or directory
make: *** [foo.o] Error 1
I get so confused with automatic variables
and pattern rules
, how to use them exactly? And do they have any relationship ?
Upvotes: 0
Views: 65
Reputation: 500
Traditional makefile syntax with all these sigils is cofusing if you're not an expert. In makepp you can use self explaining long names (and the 2nd line doesn't need to start with a tab):
%.o : %.c
gcc -c $(input) -o $(ouptut)
As for your question: while these variables are useful on all rules to avoid redundancy, they are essential on pattern rules. How else would you know which of your many input files is currently getting compiled.
There is much more to makepp. Besides doing almost all that GNU make can, there are lots more useful things, and you can even extend your makefiles with some Perl programming.
Upvotes: 0
Reputation: 46992
You're rule is wrong. It should be:
%.o : %.c
gcc -c $< -o $@
Upvotes: 1