CODEWITHSUNDEEP
caching
user1265125
user1265125

Reputation: 2656

Dealing with Multiword Block Direct Mapped Cache

I've completely understood direct mapped, associative and set associative caches but I'm stumped when I discovered Multiword block Direct Mapped cache.

Here's Q7.9 and Q7.10 of Patterson:

7.9[10] <§7.2> Here is a series of address references given as word addresses: 2,
3, 11, 16, 21, 13, 64, 48, 19, 11, 3, 22, 4, 27, 6, and 11. Assuming a direct-mapped
cache with 16 one-word blocks that is initially empty, label each reference in the
list as a hit or a miss and show the final contents of the cache.

7.10[10] <§7.2> Using the series of references given in Exercise 7.9, show the hits
and misses and final cache contents for a direct-mapped cache with four-word
blocks and a total sizeof 16 words.

7.9 is fine, it's simple. But I can't understand how 7.10 would work. It would have 4 4word size blocks. How would this be different from a 4 way set associative cache?

And if possible, can someone guide me to solving 7.10 here? I have the answer with me but I don't understand it.

Upvotes: 0

Views: 2752

Answers (1)

ArtemB
ArtemB

Reputation: 3632

In 7.10 you've got to be the cache. Draw boxes for each cache block (4 words). For each word address in sequence figure out which box it would go into. If the box already has the address, it's a hit. Otherwise it's a miss and you have to fill the box with 4 words at the current reference address aligned by cache line size.

For instance, when you're accessing word 2, you'll fill in words 0,1,2,3. Next reference for the word 3 will be a hit, because it's already in the cache. Accessing word 16 will evict the block with 0,1,2,3 in it and will fill it with 16,17,18,19...

Upvotes: 0

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