CODEWITHSUNDEEP
verilog
user2407434
user2407434

Reputation: 81

Why do I get an "Incompatible types at assignment" error in verilog?

I have the following Verilog code, why do I get the "Incompatible types at assignment"-Error for the assignment "pwmData = 4'b1000;"? I got the error in Active-HDL 9.2.

module PwmTestbench;

parameter dataWidth = 4;

reg clock, reset, pwmData[3:0], loadPwmData;
wire pwmOut;

Pwm #(.dataWidth(dataWidth)) pwm (
.clk(clock),
.reset(reset),
.data(pwmData),
.load(loadPwmData),
.out(pwmOut)
);

initial begin
    clock = 1'b1;
    reset = 1'b1;
    loadPwmData = 1'b0;
end

always begin
    #1 clock = !clock;
end

initial begin
    #1   pwmData = 4'b1000;     // # Error: VCP2852 pwm_tb.v : (29, 1): Incompatible types at assignment: .pwmData<reg[3:0]> <- 4'b1000<[3:0]bit>.
    #1   loadPwmData = 1'b1;
    #2   loadPwmData = 1'b0;
    #1   reset = 1'b0;
    #512 $finish;
end

endmodule

Upvotes: 2

Views: 2332

Answers (1)

Tim
Tim

Reputation: 35923

pwmData[3:0] defines a 4-element array of 1-bit entries.

If you want to create a 4-bit register (this is not the same as a 4x 1-bit array), than the range goes on the other side:

reg [3:0] pwmData;

Upvotes: 5

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