CODEWITHSUNDEEP
vhdl
JakobJ
JakobJ

Reputation: 1273

What is wrong with this design

I have some VHDL code which behaves strangely when synthesized, but I suspect it is my basic understanding of VHDL synthesis which is wrong.

"sync" is a short pulse (about half a clk period), which is high on clk rising edge, but shortly after goes low. During synthesis only some of the signal assignments are assigned on clk rising edge when sync is high.

Do sync need to be high for some minimum period?

process(clk)
begin
if rising_edge(clk) then
   if sync = '1' then
      a <= '1';
      y3 <= y2;
      y2 <= y1;
      y1 <= y0; 
   end if;
end if;
...

Only "a" gets its value updated, when synthesized....

Upvotes: 1

Views: 114

Answers (1)

FDinoff
FDinoff

Reputation: 31419

I can only guess since you don't show the whole of the process.

Signal do not get updated until after a process is run. So if you are using signals as intermediate variables other signals won't be updated as you expect.

if a is a signal which has value 1 before the process.
process(clk)
     ...
     a <= '0'
     a still has value 1 here
     ....
end process
a's value is now updated to 0

Upvotes: 4

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