CODEWITHSUNDEEP
makefile
Poulo
Poulo

Reputation: 1651

Conditional part of makefile always evaluating to true

I have a legacy makefile based build system that I am trying to make changes to. I am not familiar with make and so was making changes on a trial and error basis.

Not being able to deduce what the problem is I inserted this bit of code in the makefile:

ARG1 = GCC
ARG2 = ARM
ifeq($(ARG1),$(ARG2))
$(warning *** WARNING ***)
endif

When I run make, I always get the print:

   \PathToBuildDirectory\makefile.options:54:*** WARNING ***

NOTE: I am using clearmake with the -C gnu option.

How or why does the condition evaulate to true?

Upvotes: 1

Views: 325

Answers (1)

MadScientist
MadScientist

Reputation: 101111

If it behaves this way for a makefile consisting of only the above content then it's a bug in clearmake. I know that clearmake's emulation of GNU make is incomplete, but this seems pretty simple.

However, since you're already echoing an error wouldn't it be straightforward to also show the values of ARG1 and ARG2? Maybe they ARE equal. Maybe one or both are set on the command line. Maybe elsewhere one or both was assigned with the override option. Maybe clearmake is invoked with the -e option and one or both of those variables are set in the environment.

If you show their values, then you'll know.

ETA: Maybe the problem is this: in GNU make you must put a space after the ifeq, like this:

ifeq ($(ARG1),$(ARG2))

If you try your original version with GNU make, you'll get an error:

Makefile:3: *** missing separator.  Stop.

but I guess clearmake just ignores the line without any error messages.

Upvotes: 2

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