Reputation: 4975
I am striving to use generics to define a record for the interface(port
) of a component. In an older question I have been pointed to using type generics. however I do not know how to access the fields of the records. Here is an answer were the use of records with type generics is promoted
Assuming the following component:
entity genericInput is
generic(
type recordType
);
port(
result: integer;
port: in recordType
);
end entity;
architecture behav of genericInput is
begin
result <= port.part1;
end architecture;
And this instantiation:
type myRecord is record
part1: integer;
part2: std_logic_vector(1 to 100)
end record;
inst: genericInput
generic map(recordType <= myRecord)
port map(...)
i get a compilation error from modelsim:
** Error: ****.vhd(21): Unknown expanded name. --line on which i attempt port.part1
** Error: ****.vhd(22): VHDL Compiler exiting
How do I access the fields of a record supplied by generics, assuming the Record always has a field of that name (vhdl2008 is available)? (I wan't to vary the widths of the vectors in the record)?
Reworded Question: What is the best way to integrate a record with generic width vectors into the ports of an entity?
Upvotes: 0
Views: 864
Reputation: 3730
First:
PORT
is a keyword. You cannot use it as a name for your ports. If you trim your code before posting on a forum, it is greatly appreciated if you test it too. (Make it VETSMOD)Answering your question:
Inside the entity (and architecture), nothing is known about the data type. You can only access it through functions or procedurs that you pass as generic parameters. Not sure how much of this is really supported by ModelSim at this time, though.
Upvotes: 1