CODEWITHSUNDEEP
if-statementvhdl
user2475756
user2475756

Reputation: 3

VHDL Syntax error with very simple if then process

I am trying to make a simple program to turn on an LED when a button is pushed.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity TurnOn is
Port ( sig : in STD_LOGIC;
       led : out  STD_LOGIC);
end TurnOn;

architecture Behavioral of TurnOn is

(Line 39) process(sig)
begin

if sig = '1' then
led <= '1';
(Line 44) else
led <= '0';

(Line 47)end if;    
end process;
end Behavioral;

I get these errors.

Line 39: Syntax error near "process".
Line 44: Syntax error near "else".
Line 47: Syntax error near "if".

I am new to VHDL so I am assuming that it's something small that I am missing. Been staring at this for about an hour. Thanks for any input.

Upvotes: 0

Views: 7230

Answers (1)

Passepartout
Passepartout

Reputation: 442

You forgot the begin statement before your process declaration.

architecture Behavioral of TurnOn is

begin

process(sig)
begin

Upvotes: 2

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