CODEWITHSUNDEEP
c++cgccconcurrencyatomic
Clark Gaebel
Clark Gaebel

Reputation: 55

Atomic 128-bit Memory Mode Selection

Using gcc, my code has an atomic 128-bit integer than is being written to by one thread, and read concurrently from 31 threads. I don't care about operations on this variable's synchronization with any other memory in my program (i.e. I'm okay with the compiler reordering two writes to two different integers), as long as reads and writes from and to this variable are consistent. I just want the guarantee that the writes to the atomic 128-bit are "eventually" guaranteed to be reflected in the 31 threads reading from that variable.

Is it safe to use a relaxed memory model? What are the gotchas I should look out for?

Upvotes: 3

Views: 561

Answers (1)

ComicSansMS
ComicSansMS

Reputation: 54679

Relaxed ordering does not guarantee that the value written by the writer thread will ever be visible to any of the reader threads.

It is valid behavior that the readers only ever see the initial value of the variable and none of the changes. However, it is guaranteed that a writer thread always sees at least the changes he himself made to the variable (and possibly, but again not guaranteed, any later change applied by another thread).

In other words: You still get sequential consistency within a single thread, but no consistency whatsoever between different threads.

Upvotes: 3

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