CODEWITHSUNDEEP
assemblyarmconditional-statementsflagsinstruction-set
midnightBlue
midnightBlue

Reputation: 1825

Precisely when are ARM's condition flags cleared/modified?

I understand that to set them, we need to append the S, e.g.

ADDS R0,R1,R2

which will for example, set C if the result overflows.

another line of code subsequent to the previous line such as:

SUB R3,R4,R5

will make NO CHANGES whatsoever to the condition flags? (due to the lack of S )

What if the result of the current operation does not affect some condition bits? For example

ANDS R0,R1,R2

only have N,Z flags relevant to them as the result cannot generate a carry C or a signed overflow Z. In such a case, will the C,Z flags be preserved or cleared?

To see when they are set is straightforward, but I find the lectures and books I am looking at very vague in describing precisely when they can get cleared so I asked a question here to get something concrete.

Upvotes: 1

Views: 8689

Answers (4)

Simon Willcocks
Simon Willcocks

Reputation: 328

I know this is a very old question, but here's a very old summary that might help people who find it like I did.

The way the PSR flags are altered differs for logical and arithmetic operations:

Logical operations (ANDS, BICS, EORS, MOVS, MVNS, ORRS, TEQ, TST)

  • The V flag in the PSR will be unaffected.
  • The C flag will be set to the last bit shifted out by the barrel shifter, or is unchanged if no shifting took place.
  • The Z flag will be set if and only if the result is all zeroes.
  • The N flag will be set to the logical value of bit 31 of the result.

Arithmetic operations (ADCS, ADDS, CMP, CMN, RSBS, RSCS, SBCS, SUBS)

  • The V flag in the PSR will be set if signed overflow occurs (i.e. if you regard the operands as signed 32 bit integers, the signed result does not fit in a 32 bit integer); this may be ignored if the operands were considered unsigned, but warns of a possible error if the operands were 2's complement signed (the destination register is set to the bottom 32 bits of the correct unsigned result).
  • The C flag will be set to the carry out of bit 31 of the ALU, which for addition indicates that 32 bit overflow occurred, and for subtraction indicates that 32 bit underflow did not occur.
  • The Z flag will be set if and only if the result was zero.
  • The N flag will be set to the value of bit 31 of the result, indicating a negative result if the operands are considered to be 2's complement signed.

The above is quoted from http://www.riscos.com/support/developers/asm/instrset.html#62074

Upvotes: 0

arch904
arch904

Reputation: 21

This should answer your question: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204j/Cihbjcag.html.

It seems that the condition flags are never really 'automatically' reset after a certain time. They can only be updated by instructions capable of doing so. This is my understanding of:

"In ARM state, and in Thumb state on processors with Thumb-2, you can execute an instruction conditionally, based upon the ALU status flags set in another instruction, either:

  • immediately after the instruction that updated the flags

  • after any number of intervening instructions that have not updated the flags."

Upvotes: 2

Igor Skochinsky
Igor Skochinsky

Reputation: 25278

Usually yes, only the instructions with the S suffix change the flags. However, there are a few exceptions to the rule:

  • TST/TEQ and CMP/CMN instructions update flags even though the mnemonic doesn't include S.

  • In the original Thumb syntax (pre-UAL), the S suffix was omitted but most ALU instructions did change the flags. In UAL, the S suffix must be explicit for both ARM and Thumb instructions.

  • Some instruction can operate on the APSR/CPSR register directly, e.g.:

    MSR APSR_nzcvq, #0x80000000 ; set N flag, clear others

    VMRS APSR_nzcv, FPSCR ; load floating-point status word into ARM flags

    (MRC can do it too, but coprocessor usage besides VFP/NEON is deprecated)

  • exception returns (RFE, LDM or SUBS PC, LR) can change the CPSR (and thus the flags) at the place where they return to.

Upvotes: 5

old_timer
old_timer

Reputation: 71536

Please read the ARM manuals.

How is this vague?

if S == 1 then
N Flag = Rd[31]
Z Flag = if Rd == 0 then 1 else 0
C Flag = shifter_carry_out
V Flag = unaffected

Each of the flags is clearly defined. Unaffected means unaffected, it isnt touched whatever was there before will be there after. the rest are modified by ANDS

Likewise:

If S is omitted, the S bit is set to 0 and the CPSR is not changed by the instruction.

what is vague about "not changed by the instruction"?

Upvotes: 2

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