CODEWITHSUNDEEP
makefileescapinggnu-make
Achimnol
Achimnol

Reputation: 1599

Capturing filenames including parentheses with GNU Make's wildcard function

I'm going to render some plots from a set of data directories using Makefile to parallelize the process, but have problems with filename escaping with wildcard function.

This is the header of my Makefile:

SOURCE_DIR = ./results
SOURCES = $(wildcard $(SOURCE_DIR)/*cpuonly*) $(wildcard $(SOURCE_DIR)/*cudaonly*)
$(warning $(SOURCES))  # for debugging
...

The example directory names are:

Here, the output of warning function includes only the directory names without parentheses. How can I include those with parentheses as well?

EDIT: Of course, I could change the filenames NOT to include parentheses. But for this question, I'd just like to know whether using parentheses is impossible or not.

EDIT2: I tested it using filenames such as "blablah-cpuonly-(123,567).log" and the output includes them! However, it causes shell syntax error when executing the rules. :(

Upvotes: 1

Views: 619

Answers (1)

MadScientist
MadScientist

Reputation: 100856

I can't reproduce your problem (and I know of no restriction on parenthesis):

$ cat Makefile
foo := $(wildcard *foo*)
$(info foo = $(foo))
all: ;:

$ ls -1 *foo*
foo
foo-(bar,baz).bar
foo.mk

$ make
foo = foo foo-(bar,baz).bar foo.mk
:

Upvotes: 1

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