CODEWITHSUNDEEP
system-verilog
user2400361
user2400361

Reputation: 169

systemverilog: Using structure as slice specifier in streaming operations

typedef struct {
bit y;
bit x;
} t_my_unpkd_struct;

t_my_unpkd_struct a[1:0];
bit [1:0] bb[1:0];

assign { >> {a} } = { << t_my_unpkd_struct {bb} };

The above code won't compile - what am I doing wrong? Can't I use a structure as a slice specifier?

BTW, my intention is to get:

a[0].x = bb[1][0]
a[0].y = bb[1][1]
a[1].x = bb[0][0]
a[1].y = bb[0][1]

Upvotes: 2

Views: 1231

Answers (1)

Greg
Greg

Reputation: 19114

Make the struct packed and replace { >> {a} } with a:

typedef struct packed {
bit y;
bit x;
} t_my_unpkd_struct;

t_my_unpkd_struct a[1:0];
bit [1:0] bb[1:0];

assign a = { << t_my_unpkd_struct {bb} };

Simple test-bench for proof:

bit clk; always #5ns clk++;
default clocking cb @(posedge clk);
endclocking
initial begin
    repeat(20) begin
        @(negedge clk);
        void'(randomize(bb));
    end
    #10ns;
    $finish(2);
end
assert property (a[0].x == bb[1][0]);
assert property (a[0].y == bb[1][1]);
assert property (a[1].x == bb[0][0]);
assert property (a[1].y == bb[0][1]);

Updated: The following works with an unpacked struct:

assign a = { << 2 {bb} };

or

always_comb { << 2 {a} } = { << t_my_unpkd_struct {bb} };

Upvotes: 2

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