Reputation: 3753
I want to compile two slightly different versions of my C code with one Makefile.
Basically I just need to add some Flags and some source files.
Right now I have a definition for my source list:
SRC := <adding stuff>
and generating my objects from that:
OBJ = $(SRC:%.c=$(OBJS_DIR)/%.o) $(ASRC:%.s=$(OBJS_DIR)/%.o)
The "all" target should compile normally, the "iomodule" target change the vars and call "all":
.PHONY: iomodule
iomodule: CDEFS := $(subst -DFD_MODULE, -DIO_MODULE, $(CDEFS))
#iomodule: SRC += $(subst $(SRC_DIR)/,,$(wildcard $(SRC_DIR)/iomod*.c))
iomodule: SRC += iomod_ring_proto.c
iomodule: OBJ += $(OBJ_DIR)/iomod_ring_proto.o
#iomodule: $(info $(SRC))
iomodule: all
all: dirs STM32F100RB_FLASH.ld $(OBJ)
$(CC) -o $(TARGET).elf $(LDFLAGS) $(OBJ) $(LDLIBS)
$(OBJCOPY) -O ihex $(TARGET).elf $(TARGET).hex
$(OBJCOPY) -O binary $(TARGET).elf $(TARGET).bin
I had expected that "info" would print SRC including "iomod_ring_proto.c" and that OBJ, since it's a recursive variable, would include the *.o file.
Strangely, "info" prints the list without the file and "iomod_ring_proto.c" is never compiled. Yet I get a linker error that "objs/iomod_ring_proto.o" was not found. So it's not in the SRC list when I print it, not in the OBJ list when compiling, but it is in the OBJ list when linking? What's going on here??
Upvotes: 0
Views: 453
Reputation: 409266
The Make
commands like $(info)
are evaluated immediately when the makefile is loaded. That's why it shows the "global" value of $(SRC)
.
The problem with the linking not including your object file is that the the dependencies are also "evaluated" when the file is loaded. This means that for your all
target, the dependencies are set as OBJ
was when the file was loaded.
Upvotes: 1