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makefilewildcardgnu-make
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Reputation: 2220

In a Makefile, how do I define wildcard patterns?

My directory has many files with similar names: test1.cpp, test2.cpp, test3.cpp, etc. I want to compile all test files into executables test1, test2, test3, etc. They don't have to be linked to each other.

CC  = clang++
CXX = clang++

INCLUDES =

CFLAGS   = -g -Wall $(INCLUDES)
CXXFLAGS = -g -Wall $(INCLUDES)

LDFLAGS = -g
LDLIBS  =

.PHONY: default
default: test1 test2

test1:

test2:

Instead of specifying test1, test2, I want to use wildcards or pattern matching or something along those lines. How do I do this?

Upvotes: 1

Views: 811

Answers (1)

MadScientist
MadScientist

Reputation: 100836

David Rodgriquez has the right idea: make has built-in rules that will handle this for you. However I would recommend using a makefile rather than setting variables in your environment, so you can easily perform the build as another user etc. where the environment is not set up properly. Also you can use a makefile to create the default target.

This is good enough:

CC  = clang++
CXX = clang++

INCLUDES =

CFLAGS   = -g -Wall $(INCLUDES)
CXXFLAGS = -g -Wall $(INCLUDES)

LDFLAGS = -g
LDLIBS  =

.PHONY: default
default: $(basename $(wildcard test*.cpp))

That's all you need!

Upvotes: 2

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