CODEWITHSUNDEEP
makefilegnu-make
Matt
Matt

Reputation: 3852

GNU Make variable "unexpected token"

I'm working on a makefile environment for an FPGA team and I'm currently having issues with a macro. I have it defined as shown for the TOOL_EXEC variable, but I'm getting an "unexpected token" error related to the double quotes and parenthesis. If I put double double quotes the variable inflates without any quotations at all and yields no error, however our tool requires them to be in parenthesis. I need to pass the fully quoted parenthesis information, but the macro definition is giving me issues!

"syntax error near unexpected token `(' "

    Example call to tool: (This works fine)
    $ Tool --v v4.5 -odir . -verilog -vh "('name', 'propname', 'address', 'desc')" filename.rdl

    Desired Macro/variable: (not working)
    TOOL_EXEC = -odir . -verilog -vh "('name', 'propname', 'address', 'desc')"

Any Ideas? thanks

Upvotes: 0

Views: 640

Answers (2)

Beta
Beta

Reputation: 99084

Just escape every special character (e.g. quote, double quote or parenthesis) with a backslash:

TOOL_EXEC = -odir . -verilog -vh \"\(\'name\', \'propname\', \'address\', \'desc\'\)\"

Upvotes: 1

MadScientist
MadScientist

Reputation: 100781

When you set a variable in a makefile you use only the name of the variable, without the dollar sign, like this:

TOOL_EXEC = -odir . -verilog -vh "('name', 'propname', 'address', 'desc')"

If you write ${TOOL_EXEC} then it will be expanded and the result of the expansion will be used as the variable name. If it's not set, then it will resolve to:

 = -odir . -verilog -vh "('name', 'propname', 'address', 'desc')"

which is obviously not right.

Upvotes: 1

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