CODEWITHSUNDEEP
vhdlxilinx
abkds
abkds

Reputation: 1794

Implementing ROM in xilinx ( vhdl )

I am trying to implement a rom module and built a test bench for it . The check syntax for rom.vhd is showing 'correct' and it is also showing 'correct' the test bench file also , but when I click on simluate it shows some error.

Following is the code and the error which is shown . 

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
----------------

entity rom is 
port ( clk : in std_logic ;
     address : in integer range 0 to 15 ;
     data_out : out std_logic_vector( 7 downto 0 )) ;
end entity ;

------------------
architecture arch of rom is 

signal reg_address : integer range 0 to 15 ;
type memory is array ( 0 to 15 ) of std_logic_vector( 7 downto 0 ) ;
constant myrom : memory := (
2 => "11111111" , --255
3 => "11010101" , 
4 => "01101000" , 
6 => "10011011" , 
8 => "01101101" , 
9 => "00110111" , 
others => "00000000" ) ;
begin 
process(clk)
begin 
if( clk'event and clk = '1' ) then
    reg_address <= address ;
end if ;
end process ;
---------------
data_out <= myrom(reg_address) ;
 end architecture ;

testbench file :

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
----------------

entity rom_tb is 
end entity ;

-----------------------
architecture tb of rom_tb is 
component rom is 
port ( clk : in std_logic ;
     address : in integer range 0 to 15 ;
     data_out : out std_logic_vector( 7 downto 0 )) ;
end component ;
--------------------------
signal clk_tb : std_logic := '0' ;
signal address_tb : integer := 0 ; 
signal data_out_tb : std_logic_vector( 7 downto 0 ) ;
--------------------------
begin 
dut : rom port map (
    clk => clk_tb ,
    address => address_tb ,
    data_out => data_out_tb ) ;
------------------
clk_tb <= not clk_tb after 20ns ;
address_tb <= 1 after 30ns ,
                 2 after 60ns ,
                 3 after 90ns ,
                  4 after 120ns ,
                 5 after 150ns ,
                 6 after 180ns ,
                 7 after 210ns ,
                 8 after 240ns ,
                 9 after 270ns ,
                10 after 300ns ,
                11 after 330ns ,
                12 after 360ns ,
                13 after 390ns ,
                14 after 420ns ,
                15 after 450ns ;
 end architecture ;

error is :

ERROR:Simulator:29 - at 0 ns : in rom_tb(tb), file D:/VHDLPrograms/Tb/ROM/rom_tb.vhd: Default port map for entity rom to component rom connects INTEGER type local port address of the component to std_logic_vector type port of the entity.

Upvotes: 1

Views: 18463

Answers (1)

user1818839
user1818839

Reputation:

Check that the (good) testbench you have posted above is actually the one you are simulating.

If you use the Xilinx tools to generate a testbench for a VHDL entity like your ROM, it will automatically convert all your port datatypes to std_logic[_vector], so that the resulting testbench won't work until you fix it. The error you are reporting sounds as though there is more than one "rom_tb" file in your project. If that's not the problem, then try "re-run all" or "Project/Clean Project Files" then "re-run all" to eliminate out-of-date compiled versions of all your files.

EDIT: the post-route simulation has the opposite problem. The integer port has been converted to a std_logic_vector by the synth/P&R process. One solution is to create a wrapper file which looks like your "Rom" entity but where the architecture converts the address port to "unsigned" then "std_logic_vector", and passes it to the post-PAR version of the ROM.

It is good to run a post-PAR simulation once or twice, to gain confidence in the tools, but it should not be routine. Normally, behavioural simulation and post-PAR static timing analysis is good enough, unless you are chasing tool bugs (incorrect synthesis) or asynchronous logic (crossing clock domains).

Upvotes: 3

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