CODEWITHSUNDEEP
verilog
biren.K
biren.K

Reputation: 247

How do I fix the syntax error in always block

I have Verilog code:

module test;
  reg     wr,  rd;
  reg     clk, en;
  integer count=1; 
  
  initial begin
    clk = 0;
    forever #5 clk=~clk;
    en = 0;
    #5 en = 1;
    forever #10 en=~en;
  end

  always @(posedge clk && posedge en) begin //<-- Error here
    if(count %2 == 1) begin 
      wr=1;
      $display("writing");
    end
    else begin
      rd=1;
      $display("reading");
    end
  end
endmodule

This code has an error in line #14. I want to execute "always block" when both the "clk" and "en" pulses are high, but it's not working.

Upvotes: 0

Views: 257

Answers (2)

Morgan
Morgan

Reputation: 20564

The syntax you have used is very close to legal syntax but not what you intended.

Replacing && with or :

always @(posedge clk or posedge en)

This will trigger on clk and also trigger on en; this makes en an async signal. Async signals should be handled very carefully in digital design.

As @nio has suggested, what you really want to do is trigger on clk and then check if enable is high.

always @(posedge clk) begin
  if (en == 1'b1)     begin
    ..
  end
end

As a benefit as long as there is no else clause this is great syntax for use with auto clock-gate insertion by the synthesis tools.

Upvotes: 2

nio
nio

Reputation: 5289

what if you just detect positive edge for clk and test if en=1 inside a block? this is a normal way to do it... you should have one master clock and test other signals inside a block

always @(posedge clk)
begin
    if (en==1'b1)
    begin
        if(count %2 == 1)
        begin
            wr=1;
            $display("writing");
        end
        else
        begin
           rd=1;
           $display("reading");
        end
    end
end

Upvotes: 0

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