CODEWITHSUNDEEP
makefile
SeekingAlpha
SeekingAlpha

Reputation: 7817

Makefile Syntax

I am learning about makefiles and am a bit confused about some of the syntax and how SUFFIXES work.

CPP = g++
OFLAG = -o
.SUFFIXES : .o .cpp .c
.cpp.o : 
    $(CPP) $(CPPFLAGS) -c $<
.c.o :
    $(CPP) $(CPPFLAGS) -c $<

all: \
    Return \
        Declare \
    Ifthen \    
    Guess \
    Guess2 \

Return: Return.o
    $(CPP) $(OFLAG)Return Return.o

Deckare: Declare.o
    $(CPP) $(OFLAG)Declare Declare.o

# follow same format for other executables

Return.o: Return.cpp
Declare.o: Declare.cpp

# follow same format for other executables

What does the line ".SUFFIXES : .o .cpp .c" actually do?

I do not quite understand what $< means.

Where does CPPFLAGS come from? (is it a special syntax just for make?).

Upvotes: 0

Views: 355

Answers (1)

Chris Dodd
Chris Dodd

Reputation: 126508

.SUFFIXES defines the set of suffixes that make will understand for suffix rules. So with this example, you can define suffix rules involving the suffixes .o .cpp and .c. If you were to define a rule .x.o, since .x isn't in the .SUFFIXES list, it would not be a suffix rule -- it would instead be a rule to build the file .x.o

$< is short for $(<) and expands to the first dependency of the target in the current rule.

$(CPPFLAGS) is a make variable reference. Since you don't set it in this makefile, it will expand to an empty string. There's nothing particularly special about the name CPPFLAGS other than convention -- its generally the set of C pre-processor flags you want to pass to invokations of the c or c++ compiler, which is exactly how it is used here.

Upvotes: 3

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