CODEWITHSUNDEEP
makefile
Rabbitybunny
Rabbitybunny

Reputation: 367

Makefile, declare variable in executable

This is a simple question for a starter like me, but what can I do to do like the following

all: run
run:
        DIR=bin/
        $(CC) $(LIBRARY) $(INCLUDE) run.o -o $(DIR)$@

Thanks.

Upvotes: 0

Views: 346

Answers (2)

Jonathan Leffler
Jonathan Leffler

Reputation: 753565

As written, you have an assignment to the shell variable DIR on one command line. On the next line, you have the expansion of a make variable DIR. This doesn't work because the two lines are executed by different shells, and in any case, make expands $(DIR) before running the shell and DIR is not a make variable.

You could make it work like this:

all: run
run:
        DIR=bin/; \
        $(CC) $(LIBRARY) $(INCLUDE) run.o -o $${DIR}$@

The backslash means the two lines are treated as one (so much so that the semicolon is needed). The $${DIR} notation is expanded by make to ${DIR} (more precisely, $$ expands to $ and make ignores the {DIR}), and then the shell expands ${DIR} from the value set previously. You could, of course, omit the braces.

However, the answer by BeSerK is probably what you're looking for.

Upvotes: 0

BerSerK
BerSerK

Reputation: 173

Why not go like this?

DIR=bin/
all: $(DIR)/run
$(DIR)/run:
        $(CC) $(LIBRARY) $(INCLUDE) run.o -o $@

Upvotes: 1

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