Reputation: 2466
I have a folder called UnitTest. I have several .c files in it. All files contain function 'main'.
Using makefile, I want to compile all .c files of that folder together. But these files have dependency on other C files which are in different folder.
How can I write make file for this?
eg. Common\*.c - generate object file App\*.c - generate object file. - refers to .o files of Common directory UnitTest\.c - these files should be compiled as executables. Refer *.o from directory App and Common.
Update: Header files are in seperate directory called \Include
I need a single makefile for this. Please help.
Upvotes: 0
Views: 419
Reputation: 99094
This is complicated, so we will take it in stages. First, building the object files:
CFLAGS += -I/include
vpath %.h /include
This should be enough to build any object file in Common/
, Apps/
or UnitTest/
. Test this before going further.
Now to build all of the objects in Common/
:
COMMONSOURCES := $(wildcard Common/*.c)
COMMONOBJECTS := $(COMMONSOURCES:.c=.o)
all: $(COMMONOBJECTS)
Test this before going further.
Remove that all
rule, and put in a rule for the Common library. (We'll use a static library for now, since it's a little simpler.)
Common/libCommon.a: $(COMMONOBJECTS)
ar -cvq $@ $^
Test that much, tell us in the comments how it worked, then we'll build Apps
library and the UnitTest
executables.
Upvotes: 1
Reputation: 2181
As per the standards every directory will contain one Makefile. So you can have three Makefiles for this job done if you have three directories.
(d) common
|
|---(f) common.h
|---(f) common.c
|---(f) Makefile --- MAkefile for the common folder.
(d) app
|
|---(f) app.h
|---(f) app.c
|---(f) Makefile
(d) unittest
|
|---(f) unittest.h
|---(f) unittest.c
|---(f) Makefile
(f) Makefile --- invoke all makefiles in the mentioned order.
If you want one Makefile to happen all these done, you can do in that way also. Here you have to compile the files by providing paths of the files. order is most impotent.
Upvotes: 2