CODEWITHSUNDEEP
verilogsystem-verilog
Filipe Utzig
Filipe Utzig

Reputation: 121

How do I access an internal reg inside a module?

I have this architechture/topology in Verilog:

picture

How can I access the internal reg IntReg, that isn't a input/output in IntModule, in SystemVerilog?

always @(posedge clk) begin
    $display ("[Time %0t ps] IntReg value = %x", $time, DUT.IntModule.IntReg);
end

Can I use bind? How?

Upvotes: 6

Views: 5515

Answers (2)

toolic
toolic

Reputation: 62163

You don't need to use bind:

module DUT;
bit clk;
initial begin
    repeat (5) begin
        #5 clk = 0; 
        #5 clk = 1;
    end
end

always @(posedge clk) begin
    $display ("[Time %0t ps] IntReg value = %x", $time, DUT.IntModule.IntReg);
end

IntModule IntModule ();
endmodule

module IntModule;
    reg IntReg = 1;
endmodule

Output:

[Time 10 ps] IntReg value = 1
[Time 20 ps] IntReg value = 1
[Time 30 ps] IntReg value = 1
[Time 40 ps] IntReg value = 1
[Time 50 ps] IntReg value = 1

Upvotes: 2

Victor L
Victor L

Reputation: 10240

Yes, you can use interface with bind:

// Interface
interface my_if(
  input IntReg
);
endinterface: my_if

// Interface bind
bind intModule my_if my_if0(
  .IntReg(IntReg)
);

Then access the register like this:

virtual my_if _if = top.DUT.IntModule.my_if0;
$display ("[Time %0t ps] IntReg value = %x",
  $time, _if.IntReg);

Complete example with sim results on EDA Playground: http://www.edaplayground.com/s/4/115

Upvotes: 2

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