CODEWITHSUNDEEP
cgccmakefile
welahi
welahi

Reputation: 316

Makefile: multiple input files with one command

I have a poblem: My source has e.g. group1_x.c, group1_y.c, group1_z.c and group2_x.c, group2_y.c, group2_z.c.

Now my Makefile:

all: group1*.o group2*.o
    gcc -o myapp group1*.o group2*.o $(FLAGS)

group1.o:
    gcc -c group1*.c -o group1.o


group2.o:
    gcc -c group2*.c -o group2.o

Well, this doesn't work and it obviously cannot work, because there is one output file specified, but there could be ten input files! My question is now: Is it possible, to let gcc make ompile every group1*.c into a corresponding group1*.o file (without telling make, how many fies there are) and then let gcc link the stuff? I guess that's not doable with the *, is there probably somethng like "while"/"for" in make?^^

Thank you already now!

PS.: I've searched for "make", "multiple files", "multiple input", etc., but found nothing, hope that I haven't overlooked anything

Upvotes: 1

Views: 2686

Answers (2)

Beta
Beta

Reputation: 99172

This will do it:

OBJS := group1_x.o group1_y.o group1_z.o group2_x.o group2_y.o group2_z.o

myapp: $(OBJS)
    gcc -o myapp $^ $(FLAGS)

There's no need for the other rules, since Make already has a built-in rule for building foo.o from foo.c. And it's almost always a good idea to make the target of the rule the file that the rule actually builds (e.g. don't call the target all if what the rule builds is myapp).

If you want to construct the list of objects automatically (which I don't recommend), you can do it this way:

SRCS := $(wildcard group1_*.c group2_*.c)
OBJS := $(SRCS:.c=.o)

Upvotes: 1

luismartingil
luismartingil

Reputation: 1119

You can use:

CC=gcc
CFLAGS=-c
.c.o:
    $(CC) $(CFLAGS) $< -o $@

Upvotes: 0

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