CODEWITHSUNDEEP
makefile
vincegata
vincegata

Reputation: 127

I cannot figure out GNU make pattern rules example from the GNU manual

Here is the example:

     %.o : %.c
         $(CC) -c $(CFLAGS) $(CPPFLAGS) $< -o $@

At my understanding this rule finds all c-source files *.c and compiles them into object files *.o. How do I define "all" rule when I only want to compile my files into object files?

Also, if I want to build an executable how do I defile the linkage rule? Something like:

    TARGET = bsort
    CPPFLAGS = -g -Wall
    LFLAGS = 
    all: $(TARGET)

    $(TARGET): ???
    $(CC) $(LFLAGS) %.o -o $(TARGET)

     %.o : %.c
         $(CC) -c $(CFLAGS) $(CPPFLAGS) $< -o $@

So, I am trying to have two makefile using pattern rules, one makefile to compile into object files and another make file to build into executable. My projects usually have multiple source and header files.

Upvotes: 1

Views: 685

Answers (1)

MadScientist
MadScientist

Reputation: 101081

That rule doesn't find anything. It merely tells make, "if you want to build a .o file and you have a .c file available, here's the recipe you can use".

If you run make in a directory with a makefile that contains nothing but that rule, you'll get a message nothing to do because you haven't actually told make to build anything specific, you've just told it how to build something.

If you want to have an all rule that builds only object files, then you can write:

.PHONY: all
all: foo.o bar.o baz.o

Now make has a real target with real dependencies, it can use the pattern rule you defined to build those .o files.

You cannot use %.o in a recipe. Recipes are written in shell script syntax, and %.o is not shell script syntax. You could write *.o which is shell script, but that's not a good solution. Instead you should define the prerequisites of your target as the .o files to link then use the $^ automatic variable to refer to them in the recipe (see the GNU make manual section on automatic variables):

$(TARGET): foo.o bar.o baz.o
        $(CC) $(LFLAGS) -o $(TARGET) $^

Why do you want to have two different makefiles? You can put all your rules into the same makefile.

Upvotes: 1

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