CODEWITHSUNDEEP
optimizationassemblyintelsseavx
mimini
mimini

Reputation: 19

Is there a performance penalty merging MM and YMM technologies?

I have to avoid switching between SSE and AVX. I think MMs are different technology, but had to ask. Is the next code leading to penalties?:

vmovq XMM0, RAX
pinsrw MM0, EDX, 1
vmovd XMM5, EBX
movdq2q MM1, XMM2

Upvotes: 2

Views: 109

Answers (1)

Stephen Canon
Stephen Canon

Reputation: 106167

MMX registers don’t alias the low part of AVX, so there’s no state-transition hazard like there is between AVX256 and SSE.

However.

There’s really no good reason to be mixing MMX and AVX (or to use MMX at all, given that SSE is universally available and avoids several hazards associated with MMX usage, and also gives you more register names). Why are you not simply doing all of your operations in AVX (or SSE?)

Upvotes: 1

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