CODEWITHSUNDEEP
arraysverilogsystem-verilog
Arash Fotouhi
Arash Fotouhi

Reputation: 2103

Defining an array down to a nonzero constant

I have the following sub-module:

module test
(
input [LENGTH : 1] array;
);

...

endmodule

and I'm calling it from a top module as follows:

...
wire [LENGTH-1 : 0] array_top;
test test_i
(
.array (array_top);
);
...

Assume LENGTH is the same in both modules.

  1. How will array_top map to array, given array_top goes down to zero but array goes to down 1?
  2. Why would anyone define an array down to 1 and not down to 0?
  3. What will happen to array[0]?

Upvotes: 3

Views: 1508

Answers (2)

toolic
toolic

Reputation: 62019

Your questions can be answered with a small testbench:

module tb;

reg [3:0] atop;
initial begin
    $monitor("array_top=%b, array=%b", array_top, test_i.array);
    #1 atop = 4'b0000;
    #1 atop = 4'b0001;
    #1 atop = 4'b0010;
    #1 atop = 4'b0100;
end

wire [3:0] array_top = atop;
test test_i (.array (array_top));

endmodule

module test (input [4:1] array);
endmodule

Output:

array_top=xxxx, array=xxxx
array_top=0000, array=0000
array_top=0001, array=0001
array_top=0010, array=0010
array_top=0100, array=0100
  1. From your connection: array[1] = array_top[0], etc.
  2. Sometimes people want to omit connecting a signal's LSB, like an address for a memory, because the LSB has no effect.
  3. There is no array[0] signal.

Upvotes: 7

dave_59
dave_59

Reputation: 42623

When connecting ports, Verilog only cares that arrays have the same size (called an equivalent type in SystemVerilog) It does not care about the starting index value, or whether it increases or decreases. It will start by connecting the right range (LSB) of each signal. In your case array_top[0] connects to array[1]. If the sizes do not match you may get an error or warning, depending on the tool and its settings. Then the connection will either be padded or truncated after hitting the left range (MSB).

Upvotes: 2

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